As is well known, the increased complexity of mixed-signal Integrated Circuits (or IC's) makes it crucial to optimize their power consumption.
Moreover, the current market for IC's requires more and more a shift toward low voltage applications, making power consumption optimization even more critical.
For this aim, low power architectures have to be used as building blocks of a whole IC and innovative circuit topologies have to be explored.
It is also well known that the operational amplifier (or “op-amp”) is probably the most widely used building block in analog IC's, as described for instance in the article by Wang et al. entitled “Optimal design for oversampled converter” (Proc. IEEE Custom Integrated Circuit Conf., 1996, pp. 337-340).
In particular, in a wide number of applications (for example, in switched capacitor circuits or in output stage circuits), the op-amps have to charge large capacitive loads. In these cases, the op-amps have to track large signals in a limited time.
The known op-amps can be substantially divided in two main groups or classes, namely the A and AB classes of amplifiers.
Class A op-amps have poor behavior with large signals due to their constant tail current, and thus they show a transient response that is slew-rate limited, as described by Klinke et al. in the article entitled “A Very-High-Slew-Rate CMOS Operational Amplifier” (IEEE Journal of Solid-State Circuits, vol. 24, no. 3, June 1989).
In the case of large signals to be tracked, an alternative solution is thus the use of class AB op-amps, with a push-pull output stage, as described in the article by Hogervorst et al. entitled “A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries” (IEEE Journal of Solid-State Circuits, vol. 29, no. 12, December 1994).
The circuit topology described in this article, being a class AB op-amp, easily overcomes slew rate problems. However, such a circuit has a maximum output current which is not well controlled; this could be a problem in low-power applications, especially where a portable system with a battery aboard is concerned.
Yet another known solution is described by Callewaert et al. in the article entitled “Class AB CMOS amplifiers with high efficiency” (IEEE Journal of Solid-State Circuits, vol. 25, no. 3, June 1990). In this case, the proposed op-amp topology provides a boosting of the tail current of the input differential transistors for large signal operation. In this way, the current of the whole op-amp is increased in this operation state. This boosting mechanism is usually referred to as “adaptive bias”.
An op-amp topology realized according to the adaptive bias principle and able to drive a large capacitive load is described in the article by Degrauwe et al. entitled “Adaptive biasing CMOS amplifier” (IEEE Journal of Solid-State Circuits, vol. SC-17, pp. 522-528, June 1982).
However, this known solution has a problem due to the fact that the DC-gain of the op-amp so obtained is limited, since it has just one pole at high impedance on its output node.